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Younesi, R., Rastegar, J., Rastgarpour, M.. (1401). A Low-Cost Multi-Sized HEVC Core Transform Using Time-Multiplexed DCT ‎Architectures. سامانه مدیریت نشریات علمی, 10(2), 143-154. doi: 10.22098/joape.2022.9656.1675
R. Younesi; J. Rastegar; M. Rastgarpour. "A Low-Cost Multi-Sized HEVC Core Transform Using Time-Multiplexed DCT ‎Architectures". سامانه مدیریت نشریات علمی, 10, 2, 1401, 143-154. doi: 10.22098/joape.2022.9656.1675
Younesi, R., Rastegar, J., Rastgarpour, M.. (1401). 'A Low-Cost Multi-Sized HEVC Core Transform Using Time-Multiplexed DCT ‎Architectures', سامانه مدیریت نشریات علمی, 10(2), pp. 143-154. doi: 10.22098/joape.2022.9656.1675
Younesi, R., Rastegar, J., Rastgarpour, M.. A Low-Cost Multi-Sized HEVC Core Transform Using Time-Multiplexed DCT ‎Architectures. سامانه مدیریت نشریات علمی, 1401; 10(2): 143-154. doi: 10.22098/joape.2022.9656.1675

A Low-Cost Multi-Sized HEVC Core Transform Using Time-Multiplexed DCT ‎Architectures

Journal of Operation and Automation in Power Engineering
دوره 10، شماره 2، آبان 2022، صفحه 143-154    اصل مقاله (566.53 K)
نوع مقاله: Research paper
شناسه دیجیتال (DOI): 10.22098/joape.2022.9656.1675
نویسندگان
R. Younesi* 1؛ J. Rastegar1؛ M. Rastgarpour2
1Department of Electrical Engineering, Faculty of Engineering, Islamic Azad University, Saveh Branch, Saveh, Iran
2‎Department of Computer Engineering, Faculty of Engineering, Islamic Azad University, Saveh Branch, Saveh, Iran ‎
چکیده
High Efficiency Video Coding (HEVC) is one of the latest coding standards targeting high-resolution video contents. Due to the high complexity of the existing hardware implementation, this paper presents the low-cost and efficient DCT architectures for HEVC, which are able to perform DCT operation of multiple transform sizes in a single unified architecture. Our objective is to reuse the hardware resources in a DCT architectures using configurable constant multipliers as well as reducing the hardware cost and trading off between hardware complexity and efficiency. We propose three different shift-and-add units with different hardware cost and throughput. The main advantage of the proposed architectures over the existing architectures is a lower hardware and it can also perform DCT transform of different transform units which is available in HEVC standard. The experimental results over 90-nm technology show that the proposed 2D-DCT architecture #1 archives the lowest hardware cost amongst the rest of the architectures with around 57% reduction in gate count, on average. The unfolded 2D-DCT architectures #2 and #3 offer the moderate reduction in gate count around 47%, on average, with a moderate throughput. Apart from architectures #1, #2, and #3, we also develop a reusable architecture by adding an extra ( )-point DCT alongside the main DCT.
کلیدواژه‌ها
DCT؛ HEVC؛ Low-Cost؛ Multi-Sized؛ Time-multiplexed
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